Publications

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DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators

T. Glint, M. Pechimuthu and J. Mekie, "DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators," 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data

T. Glint, M. Awasthi and J. Mekie, "Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data," In Proceedings of the 29th Asia and South Pacific Design Automation Conference (ASP-DAC '24)

CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs

T. Glint, M. Awasthi and J. Mekie, "CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs," In Proceedings of the 29th Asia and South Pacific Design Automation Conference (ASP-DAC '24)

REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet

T. Glint, M. Awasthi and J. Mekie, "REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet," 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6, doi: 10.23919/DATE56975.2023.10137190.

Analysis of Quantization Across DNN Accelerator Architecture Paradigms

T. Glint, C. K. Jha, M. Awasthi and J. Mekie, "Analysis of Quantization Across DNN Accelerator Architecture Paradigms," 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-2, doi: 10.23919/DATE56975.2023.10136899.

Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators

T. Glint, C. K. Jha, M. Awasthi and J. Mekie, "Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators," 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Raleigh, NC, USA, 2023, pp. 349-351, doi: 10.1109/ISPASS57527.2023.00049.

Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA

T. Glint et al., "Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA," 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Raleigh, NC, USA, 2023, pp. 328-330, doi: 10.1109/ISPASS57527.2023.00042.

Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers

Tom Glint, Kailash Prasad, Jinay Dagli, Krishil Gandhi, Aryan Gupta, Vrajesh Patel, Neel Shah, and Joycee Mekie. 2023. Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers. In Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC '23). Association for Computing Machinery, New York, NY, USA, 469–474. https://doi.org/10.1145/3566097.3567866

ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator

T. Glint, J. Sah, M. Awasthi and J. Mekie, "ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator," 2020 IEEE 38th International Conference on Computer Design (ICCD), Hartford, CT, USA, 2020, pp. 619-622, doi: 10.1109/ICCD50377.2020.00107.